Connectionists: Nanoarch 07

[Dan Hammerstrom]

Although this conference lies somewhat outside of the general topics 
of Connectionist themes, there is a growing number of people who view 
nano-scale circuitry as being particularly well matched to 
implementing large, scalable, connectionist and neural models.

-- Dan



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The IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH '07)
                            CALL FOR PAPERS
                Santa Clara, CA October 21-22, 2007

Web site: www.nanoarch.org for more information on the symposium.

COLOCATED WITH IEEE INTERNATIONAL TEST CONFERENCE (www.itctestweek.org)

Moore's law based scaling is rapidly approaching a "brick wall" as we 
enter the nanoelectronic regime. Novel silicon and non-silicon 
nanoelectronic devices are being developed to explicitly address this 
problem. Similarly, while defect and fault-tolerance techniques are 
designed under the assumption that a system is composed largely of 
correctly functioning units, this is no longer true in emerging 
nanoelectronics. In addition, nanoelectronics offers massive 
parallelism on a scale significantly beyond anything we have seen 
before, yet very few commercial massively parallel applications are 
envisioned. Also, while current computer aided design tools and 
methodologies can barely manage billion-transistor chips, how can 
trillion-device chips that nanoelectronics promises be designed?

The purpose of the NANOARCH symposium is to be a forum for the 
presentation and discussion of novel architectures and design 
methodologies by considering these issues in future nanoscale 
implementations. The symposium seeks to build on the successes of 
NANOARCH 2005 and NANOARCH 2006. NANOARCH is interested in novel 
architectures including massively parallel, biologically inspired as 
well as those that are defect and fault tolerant, case studies on 
defect, fault and yield models, experimental reliability evaluation, 
validation frameworks, computer aided simulation, and design tools 
and emerging computational models for nanoelectronics. The 
symposium's topics of interest include:

* Architectures for nanoelectronic digital and mixed-signal circuits 
and systems
* Computational paradigms and programming models for nanoscale architectures
* Modeling and simulation of nanoelectronic devices, circuits and 
system architecture
* Simulation of complex systems with nanoscale computing architectures
* Implementing microarchitecture concepts using nanoarchitecture 
building blocks
* Defect and fault tolerant nanoelectronic device, circuit, and 
system level architectures
* Manufacture testing of nanoelectronic architectures
* Computer aided design tools and methodologies for nanoelectronic 
architectures

The Program Committee invites authors to submit papers up to 8 pages 
in length, describing original, unpublished recent work. Clearly 
describe the nature of the work, explain its significance, highlight 
novel features, and describe its current status. Electronic 
submission through the symposium website is required.

The submission of a paper proposal will be considered evidence that 
upon acceptance, the author(s) will present their paper at the symposium.

Final versions of accepted papers will be included in official 
NANOARCH symposium proceedings

IMPORTANT DEADLINE FOR NANOARCH ARE AS FOLLOWS:

Submission deadline: August 6, 2007
Acceptance Notification: Sept. 7, 2007
Final version of papers: Sept. 17, 2007

NANOARCH 2007 will have an Official Symposium Proceedings Published 
by the IEEE.

We sincerely hope you can participate in NANOARCH 2007.  Once again, 
We look forward to your submission. Should you have any questions, 
please contact one of us at the following contact addresses.

Sincerely,

Dan Hammerstrom
General Co-Chair, NANOARCH 2007
Prof. of ECE
Portland State University
strom at cecs.pdx.edu

Ramesh Karri
General Co-Chair, NANOARCH 2007
Assoc. Prof of ECE
Polytechnic University
rkarri at poly.edu
718 260 3596
917 363 9703

Alex Orailoglu
Program Co-Chair, NANOARCH 2007
Prof of CSE
Univ of Calif, San Diego
alex at cs.ucsd.edu
858 534 0914

Dr. Clifford Lau
Program Co-Chair, NANOARCH 2007
Institute for Defense Analysis
Alexandria, VA
clau at ida.org