Classifier Design for Online Handwriting Recognition

[Richard Reilly]

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            PhD/MEngSc research opportunity
  DSP Group, Electronic and Electrical Engineering Dept, UCD

     "Classifier Design for Online Handwriting Recognition"

                       02 July 1998

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Position available on ongoing project in online handwriting recognition.
Project funded by Forbairt/EU.

Tasks
This project adopts a HW/SW codesign approach to the OHR task, aiming at
implementations suitable for the constraints of PDA platform.

The Preprocessing (normalisation, feature extraction and optional segmentation)
is performed by a custom hardware module which is fully configurable by ROM and
software. The hardware development is with Synopsys compiler.

The main functions of Recognition and Postprocessing are implemented in
software, using Hidden Markov Model and Dynamic Programming methods.
Fuzzy logic may also be applied. 

C/VHDL Cosimulation will be used to define the system parameters i.e. feature
set, preprocessor and classifier functions and to benchmark the system accuracy.

Overall performance will then be validated on the UNIPEN database of online
samples. The development platform is a Solaris environment on a Sun Ultra using
the Tcl/Tk GUI.

The classifier designer will investigate the following issues:
- which classifiers perform well based on preprocessor capabilities and PDA
  constraints?
- what exact preprocessor functionality is required for the feature sets,
  with a view   to maximising invariance of the classifier to writing style
  and production?
- what types of postprocessing (lexical, syntactic, user-dependent) are
  most efficient?
- extensibility and adaptivity to multiple users, writing styles and languages
- integration of support for gestures

Requirements
- working knowledge of DSP, pattern recognition esp. HMM, DP, fuzzy methods in
  application fields such as speech, handwriting, video
- experience in C (/C++), UNIX, GUI (e.g. Tcl/Tk or Motif), MatLab
- optional experience in VLSI design with VHDL/Verilog, Synopsys compiler and
  cosimulation with C highly desirable.

Resources available
The DSP lab contains a Sun Ultra/Enterprise 450 running Solaris and Pentium/Pro
workstations using Win95.

More information on this project: http://wwdsp.ucd.ie/~stephenm

Candidates should have a good honours degree (H2.1 or H1) in a suitable area. 

Further details by contacting 
Dr Richard Reilly, Department of Electronic and Electrical Engineering
Department,
University College, Dublin 4, Ireland. 

Ph:  353 1 706 1960; 
Fax: 353 1 283 0921; 
e-mail: Richard.Reilly at ucd.ie
http://wwdsp.ucd.ie