NN chips

[ugur halici]

Dear Colleagues,

We are gathering information on Neural Network hardware devices 
that have been implemented.

Until now, we have collected sufficient information on the following 
chips/devices, for which a reference list for these devices is
provided at the end of the message:


TiNMANN Kohonen SOFM
Nestor Ni1000
Siemens MA16                
Mitsubishi Branch Neuron Unit  
Bell Labs Hopfield Chip       
Hitachi Digital Chip        
Philips  L-Neuro             
Intel ETANN               
University of Edinburgh EPSILON             
AT&T Bell Labs ANNA                
Adaptive Solution CNAPS               
Hitachi WSI                 
Siemens SYNAPSE             

However we have insufficient information on the following: 

British Telecom HANNIBAL            
Silicon Retina
Jet Propulsion Laboratory Hopfield Chip 
BELLCORE Boltzmann Machine
KAKADU Multilayer Perceptron
Fujitsu Analog-Digital Chip
U. of Catholique Louvain Kohonen SOFM Chip
MIT Neuroprocessor Chip
TRW MARK
HNC SNAP

We will appreciate your contact if you have involved somehow in implemented 
neuro-chips whose name is not in our list or listed among the ones for which 
we have insufficient information.

Sincerely,

Ugur Halici
Dept. of Electrical Engineering 
Middle East Technical University, 
06531, Ankara

Fax:   (+90) 312 210 12 61   
Email: halici at rorqual.cc.metu.edu


REFERENCES

Alspector, J.,et. al., 1989, "Performance of a Stochastic Learning Microchip.",
    Advances in Neural Information Processing Systems, Vol.1, pp. 748-760.
Arima, Y., et. al, 1991a, "A 336-Neuron, 28-K Synapse, Self-learning Neural 
    Network Chip with Branch-Neuron-Unit Architecture.", IEEE Journal of 
    Solid State Circuits, Vol.26, No.11, pp. 1637-1644.
Arima, Y., et. al, 1991b, "A Self-learning Neural Network Chip with 
    125-Neurons and 10-K self-Organization Synapses.", IEEE Journal of Solid 
    State Circuits, Vol.26, No.4,  pp. 607-611.
Arima, Y., et. al, 1992, "A Refreshable Analog  VLSI Neural Network Chip with 
    400-Neurons and 40-K synapses", IEEE Journal of Solid State Circuits, 
    Vol.27, No.12,  pp. 1854-1861.
Castro, H.A., et. al, 1993, "Implementation and Performance of Analog 
    Nonvolatile Neural Network", Analog Integrated Circuits and Signal 
    Processing, Vol.4, pp. 97-113.
Eberhardt, S.P., et.al., 1992, "Analog VLSI Neural Netowrks: Implementation 
    Issues and Examples in Optimization and Supervised Learning.", IEEE 
    Transactions on Industrial Electronics, Vol.39, No.6, pp. 552-564.
Hamilton, A., et. al, 1993, "Pulse Stream VLSI Circuits and Systems: The 
    EPSILON Neural Network Chipset", International Journal of Neural 
    Systems, Vol.4, No.4, pp. 395-405.
Holler, M., et. al, 1989, "An Electrically Trainable Artificial Neural 
   Network (ETANN) with 1024 'Floating Gate' Syanpse", Proceedings of IACNN 
   1989, pp.191-196
INTEL 80170NW ETANN Experimental Sheet, May 1990, Intel Corp.
Maher, M.A.C., et.al., 1989, "Implementing Neural Architectures Using Analog 
    VLSI Circuits.", IEEE Transactions on Circuits and Systems, Vol. 36, No. 
    5, pp. 643-652
Mueller, D., and D.Hammerstorm, 1992, "A Neural Network Systems Component", 
    Proceedings of IEEE ICNN 1992,  pp. 1258-1264.
Murray, A.F., et. al, 1994, "Pulse Stream VLSI Neural Networks.", IEEE Micro,
    June 1994, pp. 29-38.
Ramacher, U., 1992, "SYNAPSE - A Neurocomputer that Synthesizes Neural 
    Algorithms on a Parallel Systolic Engine", Journal of Parallel and 
    Distributed Computing, Vol.14, pp. 306-318.
Ramacher, U., et. al, 1993, "Multiprocessor and Memory Architecture of 
    the Neurocomputer Synapse-1", International Journal of Neural Systems, 
    Vol.4, No.4, pp. 333-336.
Sackinger, E., et. al, 1992a, "Application of the ANNA Neural Network Chip 
   to High-speed Character Recognition.", IEEE Transactions on Neural 
   Networks, Vol.3, No.3, pp. 498-505.
Tam, S., et. al, 1992, "A Reconfigurable Multi-chip Analog Neural Network 
  Recognition and Back-Propagation Training", Proceedings of IEEE ICNN 
  1992, pp. 625-630.
Watanebe, T., et. al, 1993, "A Single 1.5V Digital Chip for a 106 Synapse 
  Neural Network.", IEEE Transactions on Neural Networks, Vol.4, No.3, pp. 
  387-393.