papers in neuroprose

Bernabe Linares B. bernabe at cnm.us.es
Tue Feb 7 04:40:21 EST 1995


FTP-host: archive.cis.ohio-state.edu
FTP-file: pub/neuroprose/bernabe.art1chip.ps.Z

The file bernabe.art1chip.ps.Z is now available for
copying from the Neuroprose repository. It contains 2 conference
papers (the PostScript file prints in 14 pages):

Title Paper1: A Real Time Clustering CMOS Neural Engine
Title Paper2: Experimental Results of An Analog Current-Mode ART1 Chip
Authors: T. Serrano, B. Linares-Barranco, and J. L. Huertas
Filiation: National Microelectronics Center (CNM), Sevilla, SPAIN.

Sorry, no hardcopies available.

Paper1 will appear in the 7th NIPS Volume, and Paper2 has been accepted
for presentation at the 1995 IEEE Int. Symp. on Circuits and Systems,
Seattle, Washington (ISCAS'95, April 29-May 3).
These and related papers can also be obtained through anonymous ftp
from the node "ftp.cnm.us.es" and directory "/pub/bernabe/publications".
The following abstract describes briefly the topic of the two papers.

ABSTRACT:
In these papers we present a real time neural categorizer chip based on
the ART1 algorithm. The circuit implements a modified version of the
original ART1 algorithm more suitable for VLSI implementations. It
has been designed using analog current-mode circuit design techniques, and
consists basically of current mirrors that are switched ON and OFF
according to the binary input patterns. The chip is able to cluster 100
binary pixels input patterns into up to 18 different categories. Modular
expansibility of the system is possible by simply interconnecting more
chips in a matrix array. This way a system can be built to cluster NX100
binary pixels images into MX18 different clusters, using an NXM array of
chips. Avarage pattern classification is performed in less than 1.8us, which
means an equivalent computing power of 2.2X10^9 connections per second
and connection updates per second.
The chip has been fabricated in a single-poly double-metal 1.5um standard
digital low cost CMOS process, has a die area of 1cm^2, and is mounted in
a 120 pins PGA package. Although the circuit is analog in nature, it is
full-digital-compatible since it interfaces to the outside world through
digital signals.



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