Neural Network reports available

[Heini Withagen]

The following neural network related reports are available from ftp.urc.tue.nl
in the /neural directory. Send any questions to: heiniw at eeb.ele.tue.nl


neural_interface.ps.gz:

                INTERFACING NEURAL NETWORK CHIPS
                    WITH A PERSONAL COMPUTER

                      J.J.M. van Teeffelen 

                             Abstract:

The Electronic Circuit Design Group at the Eindhoven University of Technology
currently is implementing several neural networks with a multi-layered
perceptron architecture together with their learning algorithms on VLSI
chips. In order to test these chips and to use them in an application they
will be connected with a personal computer with the help of an interface.

This interface, that has to be as versatile as possible, meaning that is must
be able to connect all kinds of neural network chips to it, can be realized
either by making use of commercially available interfaces or by designing an
own interface with help of off-the-shelf components. Two interfaces will be
discussed, one for the rather slow AT-bus and one for the high speed VESA
local bus.

Although the commercially available interfaces are not as versatile as
wished, and the prices may seem rather high, they turn out to be the best way
to realize the interface at the moment. They are guaranteed to work and can
be used immediately. The discussed interfaces for the AT-bus and the VESA
local bus still have to be tested and implemented on a printed circuit board.

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weight_perturbation.tar.gz:

                A STUDY OF THE WEIGHT PERTURBATION 
                ALGORITHM USED IN NEURAL NETWORKS

                          R.E. ten Kate

                             Abstract:

This thesis studies different aspects of the Weight Perturbation (WP) algorithm
used to train neural networks.

After a general introduction of neural networks and their algorithms, the WP
algorithm is described. A theoretical study is done describing the effects of
the applied perturbation on the error performance of the algorithm. Also a
theoretical study is done describing the influence of the learning rate on the
convergence speed. The effects of these two algorithm parameters have been
simulated in an ideal Multilayer Perceptron using various benchmark problems.

When the WP algorithm is implemented on an analog neural network chip,
several hardware limitations are present which influence the performance of
the WP algorithm; weight quantization, weight decay, non-ideal multipliers
and neurons. The influence of these non-idealities on the algorithm
performance has been studied theorectically. Simulations of these effects
have been done using predicted parameters by SPICE simulations of the
hardware. Several proposals are made to reduce the effects of the hardware
non-idealities.

Two proposals have been studied to increase the speed of the WP algorithm.

 
Heini Withagen
Dep. of Elec. Engineering EH 9.29         
Eindhoven University of Technology        
P.O. Box 513                              Phone: 31-40472366
5600 MB Eindhoven                         Fax:   31-40455674
The Netherlands                           E-mail: heiniw at eeb.ele.tue.nl

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