Six papers available by ftp

[Jaap Murre]

Six reports by the Leiden Connectionist Group have recently been
placed in our ftp site. Retrieval instructions can be found at the
end of this message. -- Jaap Murre


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File: modann1.ps.Z

Title: Designing Modular Artificial Neural Networks

Authors: Egbert J.W. Boers, Herman Kuiper, Bart L.M. Happel, and 
Ida G. Sprinkhuizen-Kuyper

Abstract:
This paper presents a method for designing artificial neural network 
architectures. The method implies a reverse engineering of the processes
resulting in the mammalian brain. The method extends the brain
metaphor in neural network design with genetic algorithms and
L-systems, modelling natural evolution and growth. It will be argued
that a principle of modularity, which is inherent to the design method as
well as the resulting network architectures, improves network
performance.

E-mail comments to boers at WI.LeidenUniv.nl or to
happel at rulfsw.LeidenUniv.nl


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File: bsp400.ps.Z

Title: The BSP400: A Modular Neurocomputer

Authors: Jan N.H. Heemskerk, Jaap Hoekstra, Jacob M.J. Murre, 
Leon H.J.G. Kemna, and Patrick T.W. Hudson

Abstract:
This paper discusses the main architectural issues, the implementation,
and the performance of a parallel neurocomputer, the Brain-Style
Processor or BSP400. This project presents a feasibility study for larger
parallel neurocomputers. The design principles are hardware modularity,
simple processors, and in situ (local) learning. The modular approach of
the design ensures extensibility of the present version. The BSP400
consists of 25 Modules (boards) each containing 16 simple 8-bit
single-chip computers. The Module boards are connected to a dedicated
connection network. The architectural configuration of the BSP400
supports local activation and learning rules. The ability to communicate
activations with the outside world in real-time makes the BSP400
particularly suited for real-world applications. The present version
implements a modular type of neural network, the CALM (Categorizing
And Learning Module) neural network. In this implementation of
CALM, activations are transmitted as single bits, but an internal
representation of one byte is kept for both activations and weights. The
system has a capacity of 400 processing elements and 32,000
connections. Even with slow and simple processing elements, it still
achieves a speed of 6.4 million connections per second for a
non-learning CALM network. Some small network simulation studies
carried out on the BSP400 are reported. A comparison with a design
study (Mark III and Mark IV) is made.

E-mail comments to HMSKERK at rulfsw.LeidenUniv.nl


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File: schema.ps.Z

Title: A Real-Time Neural Implementation of a Schema Driven Toy-Car

Authors: Jan N.H. Heemskerk and Fred A. Keijzer

Abstract:
An actual implementation of a schema driven toy-car is presented in this
paper. The car is equipped with two motors and 4 light sensors.
Supervised learning behavior of the car is achieved by using a neural
network with adaptive connections. The car can be taught to drive
towards a light and avoid obstacles. The controlling neural network is
implemented on the BSP400 neurocomputer, a Brain Style Processor
with 400 nodes. A subset of the digital nodes in the BSP400 are
connected by fixed weights to form logical circuits in order to re-train
the car. In this way cooperative computation of both 'logical' and
'neural' processes are integrated into one system. The actions of the car
are described in terms of both distal and proximal schemas. These
correspond respectively with a description of the car's actions in terms
of distal system environmental stimuli and effects, and a description of
the local routines carried out by the system. The latter are restricted to
the specific situatedness and embodiment of the acting system. The
distinction between  distal and proximal schemas is presented as a way
to link neural structure to adaptive action.

E-mail comments to HMSKERK at rulfsw.LeidenUniv.nl 


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File: mindshap.ps.Z

Title: MindShape: a neurocomputer concept based on a fractal
architecture

Authors: Jan N.H. Heemskerk, Jacob M.J. Murre, Arend Melissant,
Mirko Pelgrom, and Patrick T.W. Hudson

Abstract:
A parallel architecture for implementing massive neural networks, called
MindShape, is presented. MindShape is the successor to the Brain Style
Processor, a 400-processor neurocomputer based on the principle of
modularity. The MindShape machine consists of Neural Processing
Elements (NPEs) and Communication Elements (CEs) organized in what
we have called a fractal architecture. The architecture is by definition
scalable, permitting the implementation of very large networks
consisting of many thousands of nodes. Through simulations of data-
communication flow on different architectures, and through
implementation studies of VLSI hardware on a chip simulator, the
specific requirements of the CEs and the NPEs have been investigated. 

E-mail comments to HMSKERK at rulfsw.LeidenUniv.nl 


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File: optim.ps.Z

Title: Implementation of Optimization Networks in Synchronous
Massively Parallel Hardware

Authors: Jan N.H. Heemskerk, Peter A. Starreveld, 
and Patrick T.W. Hudson

Abstract:
In this paper, implementation possibilities of a synchronous binary
neural model for solving optimization problems in massively parallel
hardware are studied. It is argued that synchronous, as opposed to
asynchronous models are best suited to the general characteristics of
massively parallel architectures. In this study the massively parallel
target device is the BSP400 (Brain Style Processor with 400 nodes). The
updating of the nodes in the BSP400 is synchronous and the nodes can
only process local data (i.e., activations). The synchronous models
studied were introduced by Takefuji [7] and make use of both local and
global operators. The functionality of these operators with regard to the
quality of the solutions was examined through software simulations.
Fully digital neurocomputers such as the BSP400 offer sufficient
flexibility for programming local operations on node level. The
possibilities of translating the function of global operators into local
operations were also studied. The aim of this study is to combine
massively parallel hardware with synchronous neural networks models
for optimization problems in order to get both high speed and high
quality of the solutions. 

E-mail comments to HMSKERK at rulfsw.LeidenUniv.nl 


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File: pictwrd.ps.Z

Title: A Connectionist Model for Context Effects in the Picture-Word
Interference Task

Authors: Peter A. Starreveld and Jan N. H. Heemskerk

Abstract:
In the picture-word interference task, two context effects can be distin-
guished: the semantic interference effect and the orthographic facilitation
effect. A theory is described to explain these effects. This theory was
implemented in a connectionist model. The model is able to simulate the
time courses of the two context effects and their interaction.

E-mail comments to STARREVE at rulfsw.LeidenUniv.nl 



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