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[Marwan Jabri]

	***************** Technical Report Available *****************

		 Predicting the Number of Vias and Dimensions
	  of Full-custom Circuits Using Neural Networks Techniques 

		       Marwan Jabri & Xiaoquan Li
	  	    School of Electrical Engineering
			University of Sydney

		        marwan at ee.su.oz.au
		   (SEDAL Tech Report 1991-1-6)

Abstract 

Block layout dimension prediction is an important activity in many
VLSI design tasks (structural synthesis, floorplanning and physical
synthesis).  Block layout {\em dimension} prediction is harder than
block {\em area} prediction and has been previously considered to be
intractable [Kurdahi89]. In this paper we present a solution
to this problem using a neural network machine learning paradigm. 
Our method uses a neural network to predict first the number of
vias and then another neural network that uses this prediction and
other circuit features to predict the width and the height of the layout of the
circuit. Our approach has produced much better results than those published,
{\em dimension} (aspect ratio) prediction average error of 
less than 18\% with corresponding {\em area} prediction average 
error of less than 15\%. Furthermore, our technique predicts the 
number of vias in a circuit with less than 4\% error on average.

*** Also submitted

To ftp this report:
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>binary
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>get jabri.dime.ps.Z 
>quit

uncompress jabri.dime.ps.Z
lpr -P<name of your laser printer> jabri.dime.ps 

If for any reasons you are unable to print the file, you can ask for a
hardcopy by writing to (and asking for SEDAL Tech Report 1991-1-6):

Marwan Jabri
Sydney University Electrical Engineering
NSW 2006 Australia