NIPS VLSI post conference workshop

[Jim Burr]

This year's post conference workshop on VLSI neural nets will be held
Saturday, Dec 1. There will be a morning and an evening session.
The workshop will address the latest advances in VLSI
implementations of neural nets. How successful have implementations been so
far? Are dedicated neurochips being used in real applications?  What
algorithms have been implemented? Which ones have not been? Why not?  How
important is on chip learning? How much arithmetic precision is necessary?
Which is more important, capacity or performance? What are the issues in
constructing very large networks? What are the technology scaling limits?
Any new technology developments?

Several invited speakers will address these and other questions from various
points of view in discussing their current research. We will try to gain
better insight into the strengths and limitations of dedicated hardware
solutions.

	Jim Burr
	burr at mojave.stanford.edu