NIPS VLSI workshop
Joshua Alspector
josh at flash.bellcore.com
Thu Nov 9 14:54:04 EST 1989
The following is an announcement for one of the workshops
to be held December 1-2, 1989 at the Keystone resort
after the NIPS-89 conference.
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VLSI NEURAL NETWORKS:
CURRENT MILESTONES AND FUTURE HORIZONS
Moderators:
Joshua Alspector and Daniel B. Schwartz
Bell Communications Research GTE Laboratories, Inc.
445 South Street 40 Sylvan Road
Morristown, NJ 07960-19910 Waltham, MA 02254
(201) 829-4342 (617) 466-2414
e-mail: josh at bellcore.com e-mail: dbs%gte.com at relay.cs.net
This workshop will explore the potential and problems of VLSI
implementations of neural network. Several speakers will discuss
their implementation strategies and speculate about where their work
may lead. Workshop attendees will then be encouraged to organize
working groups to address specific issues raised in connection with
the presentations. An example of a topic that has lead to contentious
discussion in the past is the relative virtue of analog vs. digital
implementations of neural networks. Some other possible topics
include:
o Architectural issues
- synchronous or asynchronous
- full time or multiplexed interconnect
- local or global connectivity
o Technological issues
- neural network specific VLSI technololgies
- design tools and methodologies
- robustness/fault tolerance
o Theoretical issues
- model of analog computation
- complexity
As part of the working groups, we also expect to make contact with
deeper issues such as the limits to VLSI complexity for neural
networks, the nature of VLSI compatible neural network algorithms, and
which neural network applications demand special purpose hardware.
Speakers (besides the moderators) include:
Jay Sage - MIT-Lincoln Lab
Rod Goodman - Caltech
Bernhard Boser - AT&T/Bell Labs
Alan Kramer - UC Berkeley
Jim Burr - Stanford
Nelson Morgan - ICSI
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