<div dir="ltr"><p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><b><span lang="EN-US"><br></span></b></p><p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><b><span lang="EN-US">Senior Embedded System AI Researcher</span></b></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">The Embedded Artificial Intelligence Laboratory of CEA LIST (<a href="http://list.cea.fr">list.cea.fr</a>)
is looking for an experienced and passionate Senior AI Embedded System Engineer
to join full time our team in Paris-Saclay.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">He/She
will be working with scientists and engineers to develop innovative solutions
for embedded AI, in particular in the field of intelligent imagers and embedded
computing architectures for vision systems. </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">Within our
team, his/her main tasks will be:</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Propose
and design innovative and efficient embedded computing architectures capable of
supporting state-of-the-art vision and AI algorithms;</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Contribute to the roadmap of the laboratory by providing expertise on these
topics and by keeping up to date with the state of the art;</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Participate in the scientific dissemination of the team's research results for
example by publishing in leading international conferences and journals;</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Supervise doctoral and master students and/or end-of-study inters;</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Contribute to the technical content for the setting up of national or European
research projects as well as for the establishment of our future work with
industrial partners.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">Moreover,
he/she can participate in some of the research topics addressed in the team
such as:</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Design
of performance and energy efficient embedded computing hardware architectures.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* High-level
hardware modeling and synthesis.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Architecture and algorithm optimization (Algorithm Architecture Adequacy);</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">Candidate’s
profile</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* A
minimum of a Masters degree in Embedded Systems Engineering, Electronic
Engineering. A PhD is preferred.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* 5+ years
of demonstrated, hands on, professional experience in the field of embedded
systems for artificial intelligence.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Experience
in research and/or design of hardware architecture on FPGA or ASIC, preferably
in the field of computer vision.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">Required
technical skills:</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Solid
knowledge of programmable digital embedded systems architecture (processors,
memory hierarchy, Caches, NoCs, etc.)</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Knowledge of Front End ASIC/FPGA design tools and flows (Vivado, QuestaSim,
VCS, Design Compiler, etc.)</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* A good
understanding of RTL description languages: VHDL, Verilog, SystemVerilog or UVM</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* The
ability to conduct a research project independently, and to write and publish
scientific papers in international conferences and journals</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Knowledge of neural networks, for example for computer vision or time sequence
processing</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Ability
to work and communicate in French with all levels of the organization (verbal,
written, and presentations)</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Desire
and ability to solve complex problems and challenges, and to produce results in
a fluid, dynamic, and fast-paced environment</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Good
knowledge of spoken and written French and English</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">Desired
experiences or skills:</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">*
Consistent experience in ASIC/FPGA hardware architecture development and
validation;</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Good
knowledge of computer vision algorithms and/or intelligent imagers</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Mastery
of software development tools and approaches: version management (Git),
compilation, testing strategies</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Strong
programming skills in C/C++ and/or Python</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Notion
in ASIC CMOS visible or infrared imager fabrication technology.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">Advantages
of working at CEA</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* A unique
research environment with exceptional experimental resources dedicated to
ambitious projects to address today's major scientific challenges.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* An
experience at the cutting edge of innovation, with a strong potential for
industrial development.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* A well balanced private/professional life (more than 40 days of paid holiday per year).</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Diversity
and inclusion policies.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Competitive
salary (between French Level E3 and E5)</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Generous
productivity bonuses</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Additional
private medical insurance</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span style="font-size:11pt">* Social
security / Pension program</span><br></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Partial transport reimbursement</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">* Partial smart-working options</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">About CEA and CEA LIST</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">The CEA (Commission for Alternative Energies and
Atomic Energy, <a href="http://www.cea.fr">www.cea.fr</a> ) is a French public government-funded research
organization in the areas of energy, defense and security, information, communication
and health technologies. The CEA maintains a cross-disciplinary culture of
engineers and researchers, building on the synergies between fundamental and
technological research, and has the mission of maturing and transferring
technology from theoretical proof of concept to industrial demonstrator for the
benefit of industry. It has about 20’500 employees and an annual budget of
about 5 billion euros.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">CEA LIST, is a research laboratory specialized in
intelligent digital systems, is one of the three institutes of CEA Tech, along
with CEA LETI and CEA LITEN. CEA List is located in the heart of the Paris-Saclay
science, technology and university cluster, which will soon house nearly a
quarter of France's scientific research, with a first-class urban campus and
infrastructure integrated into the Greater Paris area.</span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US"> </span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="EN-US">Contact person: </span><span lang="EN-US">BICHLER Olivier </span><span lang="EN-US"><a href="mailto:olivier.bichler@cea.fr" style="color:rgb(5,99,193)">olivier.bichler@cea.fr</a></span><span class="gmail-MsoHyperlink" style="color:rgb(5,99,193);text-decoration-line:underline"><span lang="EN-US"><span class="gmail-msoIns" style="color:teal"><ins cite="mailto:BICHLER%20Olivier" datetime="2023-03-28T09:34"></ins></span></span></span></p>
<p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="FR"><br></span></p><p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><span lang="FR">Apply on
CEA’s Carrier Site: <a href="https://www.emploi.cea.fr/offre-de-emploi/emploi-chercheur-se-en-architectures-materielles-embarquees-pour-intelligence-artificielle-ia-h-f_22079.aspx" style="color:rgb(5,99,193)">https://www.emploi.cea.fr/offre-de-emploi/emploi-chercheur-se-en-architectures-materielles-embarquees-pour-intelligence-artificielle-ia-h-f_22079.aspx</a></span></p><p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><br></p><p class="MsoNormal" style="margin:0cm 0cm 0.0001pt;line-height:120%;font-size:11pt;font-family:Calibri,"sans-serif""><br></p></div>