two papers in neuroprose

Bernabe Linares B. bernabe at cnm.us.es
Tue Dec 12 07:39:41 EST 1995


FTP-host:  archive.cis.ohio-state.edu
FTP-file:  pub/neuroprose/bernabe.art1-nn.ps.Z (30 pages, 257846 bytes)
           pub/neuroprose/bernabe.art1-vlsi.ps.Z (26 pages, 311686 bytes)

The files "bernabe.art1-nn.ps.Z" and "bernabe.art1-vlsi.ps.Z" are now
available for copying from the Neuroprose repository. They contain two
papers which have been accepted for publication in the following journals:

PAPER1:  Journal: IEEE Transactions on VLSI Systems
         Title: "A Real-Time Clustering Microchip Neural Engine"
         File: bernabe.art1-vlsi.ps.Z

PAPER2:  Journal: Neural Networks
         Title: "A Modified ART1 Algorithm more suitable for VLSI
                 Implementations"
         File: bernabe.art1-nn.ps.Z

Authors: Teresa Serrano-Gotarredona and Bernabe Linares-Barranco
Filiation: National Microelectronics Center (CNM), Sevilla, SPAIN.

Sorry, no hardcopies available.


Brief description of papers follows:

--------------------------------------------------------------------
PAPER1:
-------

File: bernabe.art1-vlsi.ps.Z, 26 pages, 311686 bytes.

Title: "A Real-Time Clustering Microchip Neural Engine"

                            Abstract
This paper presents an analog current-mode VLSI implementation of an
unsupervised clustering algorithm. The clustering algorithm is based on the
popular ART1 algorithm [1], but has been modified resulting in a more
VLSI-friendly algorithm [2], [3] that allows a more efficient hardware 
implementation with simple circuit operators, little memory requirements,
modular chip assembly capability, and higher speed figures. The chip described
in this paper implements a network that can cluster 100 binary pixels input
patterns into up to 18 different categories. Modular expansibility of the 
system is directly possible by assembling an NxM array of chips without any
extra interfacing circuitry, so that the maximum number of clusters is 18xM
and the maximum number of bits of the input pattern is Nx100. Pattern
classification and learning is performed in 1.8us, which is an equivalent
computing power of 4.4x10^9 connections per second plus connection-updates
per second. The chip has been fabricated in a standard low cost 1.6um
double-metal single-poly CMOS process, has a die area of 1cm^2, and is mounted
in a 120-pin PGA package. Although internally the chip is analog in nature,
it interfaces to the outside world through digital signals, and thus has a true
asynchronous digital behavior. Experimental chip test results are available,
obtained through digital chip test equipment. Fault tolerance at the system
level operation is demonstrated through the experimental testing of faulty
chips.

--------------------------------------------------------------------
PAPER2:
-------

File: bernabe.art1-nn.ps.Z, 30 pages, 257846 bytes.

Title: "A Modified ART1 Algorithm more suitable for VLSI Implementations"

                          Abstract
This paper presents a modification to the original ART1 algorithm
[Carpenter, 1987a] that is conceptually similar, can be implemented in hardware
with less sophisticated building blocks, and maintains the computational
capabilities of the originally proposed algorithm. This modified ART1 
algorithm (which we will call here ART1m) is the result of hardware motivated
simplifications investigated during the design of an actual ART1 chip
[Serrano, 1994, 1996]. The purpose of this paper is simply to justify
theoretically that the modified algorithm preserves the computational
properties of the original one and to study the difference in behavior
between the two approaches.

--------------------------------------------------------------------
ftp instructions are:

% ftp archive.cis.ohio-state.edu
Name : anonymous
Password: <your e-mail address>
ftp> cd pub/neuroprose
ftp> binary
ftp> get bernabe.art1-nn.ps.Z  
ftp> get bernabe.art1-vlsi.ps.Z
ftp> quit
% uncompress bernabe.art1-nn.ps.Z
% uncompress bernabe.art1-vlsi.ps.Z
% lpr -P<your_printer> bernabe.art1-nn.ps
% lpr -P<your_printer> bernabe.art1-vlsi.ps

These files are also available from the node "ftp.cnm.us.es", user
"anonymous", directory /pub/bernabe/publications,
files: "NN_art1theory_96.ps.Z" and "TVLSI_art1chip_96.ps.Z".

Any feedback will be appreciated. Thanks,

Dr. Bernabe Linares-Barranco
National Microelectronics Center (CNM)
Dept. of Analog Design
Ed. CICA, Av. Reina Mercedes s/n, 
41012 Sevilla, SPAIN.
Phone: 34-5-4239923, Fax: 34-5-4624506, 
E-mail: bernabe at cnm.us.es



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