paper available on neural hardware

[Bernabe Linares B.]

FTP-host: archive.cis.ohio-state.edu
FTP-file: pub/neuroprose/bernabe.art1chip.ps.Z

The file bernabe.art1chip.ps.Z is now available for
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Title: A CMOS VLSI Analog Current-Mode High-Speed ART1 Chip (4 pages)
Authors: T. Serrano, B. Linares-Barranco, and J. L. Huertas
Filiation: National Microelectronics Center (CNM), Sevilla, SPAIN.

This paper is going to appear in the ICNN'94 proceedings, and it is
going to be presented at the ICNN'94 meeting, Orlando, Florida, the
28th of June, in the Special Invited Session "Advanced Analog Neural
Networks and Applications", at 8:20am (according to the preliminary
program).


ABSTRACT:
In this paper we present a real time neural categorizer chip based on
the ART1 algorithm [1]. The circuit implements a modified version of the
original ART1 algorithm more suitable for VLSI implementations [2]. It
has been designed using analog current-mode circuit design techniques, and
consists basically of current mirrors that are switched ON and OFF
according to the binary input patterns. The chip is able to cluster 100
binary pixels input patterns into up to 18 different categories. Modular
expandability of the system is possible by simply interconnecting more
chips in a matrix array. This way a system can be built to cluster NX100
binary pixels images into MX18 different clusters, using an NXM array of
chips. Avarage pattern classification is performed in less than 1us, which
means an equivalent computing power of 1.8X10^9 connections per second.
The chip has been fabricated in a single-poly double-metal 1.5um standard
digital low cost CMOS process, has a die area of 1cm^2, and is mounted in
a 120 pins PGA package. Although the circuit is analog in nature, it is
full-digital-compatible since all its inputs and outputs are digital.

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